The invention relates to a semiconductor device, and more particularly, to patterning fins of a FinFET semiconductor device.
Interests in multi-gate MOSFETs have significantly increased as the industry continues to demand smaller sized MOSFET devices. One such device that is capable of maintaining industry performance standards at a reduced size is the FinFET.
A conventional FinFET includes one or more fins that are patterned on a substrate, such as a silicon-on-insulator (SOI) substrate. For example, a conventional sidewall image transfer (SIT) process can be used to form a dense array of fins surrounded by silicon oxide layer, and a dummy gate patterning process is performed for forming a gate after forming the fins. Conventional FinFET fabrication processes perform a silicon (Si) epitaxial (epi) merging process to merge the fins after forming the dummy gate. However, the selective epi Si growth process is difficult to control and hence is unstable. The control difficulties typically cause the epi Si to grow at different thicknesses on individual fins of the same wafer or between processing runs of different wafers. Thus, this inconsistent growth can result in the epi Si being inconsistently thicker or thinner.